1. Field of the Invention
This invention relates to an I/O interface circuit capable of carrying out rapid data transmission, a semiconductor chip having this I/O interface circuit and a semiconductor system provided with a plurality of the semiconductor chips.
2. Description of the Prior Art
In recent years, the performance of high-performance LSI such as a micro processor has been rising rapidly. This rise of the performance is supported by application of high frequency internal clock by process scaling or introduction of pipeline method.
On the other hand, currently, signal transmission between chips cannot meet this application of high frequency internal clock inside the chip sufficiently. In a conventional TTL/LV-TTL I/O interface, signal transmission with high frequency wave of more than 100 MHz is difficult to realize due to crosstalk, simultaneous signal switching noise (SSN), reflection of signal in transmission path and the like. Therefore, the TTL/LV-TTL interface and the like is a bottleneck of the performance of a high performance LSI.
If the signal transmission speed between the chips is not increased, a trend of multiple pins is indispensable for securing a band width, so that this largely influence production, mounting work, and board cost. Therefore, in the high-performance LSI field, an I/O interface capable of high speed signal transmission has been introduced gradually.
FIGS. 1A-1C show a TTL/LV-TTL I/O interface which has been generally used in a conventional art. FIG. 1A is a structure diagram thereof, FIG. 1B is a potential waveform diagram upon "H" level transmission, and FIG. 1C is a current waveform diagram upon "H" level transmission.
When for example, "H" level is transmitted from a chip 110 of TTL to a chip 120 of LV-TTL through a transmission path 101, P channel MOSFET 112 and N channel MOSFET 113 constituting an I/O buffer 111 of the chip 110 are both turned on. As a result, current flowing through the transmission path 101 changes as shown in FIG. 1C and with an convergence of current amount, the potential is stabilized on VDDQ level as shown in FIG. 1B. Then, on the side of the chip 120, the "H" level signal of the transmission path 101 is received by a differential amplifier 121.
Because the side of the chip 120 in input mode becomes an open end in this I/O interface, signal reflection occurs in the transmission path 101 so that transmission waveform is distorted. Further, because the logical amplitude is large, noise due to dI/dt occurs in high speed operation. Thus, in the high speed I/O interface, generally, the transmission path is terminated.
FIGS. 2A-2E show high speed interface circuits of conventional various terminating types. FIG. 2A shows a GTL/RSL interface, FIG. 2B shows a push-pull type HSTL interface, FIG. 2C shows a SSTL interface, FIG. 2D shows a CTT interface and FIG. 2E shows a LVDS interface.
Because terminating resistors 201, 301, 401, 501, 601 are mounted on a board in the vicinity of the chip 2, if signal is transmitted from the chip 1 to the chip 2, signal reflection at a buffer portion of the chip 2 in input mode is suppressed. Further, because dI/dt can be set small as well as the logical amplitude is small, there does not occur much noise.
FIG. 3 is a structure diagram showing a conventional high-speed interface circuit disclosed in Japanese Patent Application Laid-Open No.8-204539.
In the same Figure, reference numeral 710 denotes a transmission path, numerals 711-714 denote a terminating resistor, numerals 720, 730, 740, 750 denote a chip, numeral 731 denotes a resisting element control means, and numerals 732, 733 denote an on chip terminating means comprising N-MOSFET.
Because in an open drain I/O interface circuit, a large reflection occurs in the transmission path when that circuit is driven from "L" level to "H" level, in this example, the signal sending side is driven by a push-pull buffer (on chip terminating resistor means 732, 733) complementarily so as to keep the sending side chip end of the transmission path 710 from being open.
However, the above first conventional I/O interface circuit has such a problem that a terminating resistor is required to be provided on the board to prevent reflection by an open end thereby producing a high cost.
Although in the respective examples shown in FIGS. 2A-2E, the description is made on an assumption of transmission of a signal in a single direction between two chips, in case of both-way transmission of a signal between two chips, the terminating resistor is required to be inserted in the vicinity of each chip (parallel termination). This reason is that if signal transmission is carried out from the chip 2 to the chip 1, the side of the chip 1 becomes an open end so that a distortion of waveform due to reflection occurs. In such a parallel termination, in the conventional example, two terminating resistors are needed on the board.
Further, in an ordinary system, as well as a point-to-point connection shown in the conventional example, branch/stub connections each having a branch in transmission path have been widely used. In this case, if the parallel termination is carried out to prevent reflection by the open end, in the conventional example, a same number of terminating resistors as that of chips are required to be mounted on the board.
In the aforementioned patent case, the terminating resistors 711-714 on the transmission path cannot be removed.
As described above, if it is intended to realize a high speed I/O interface circuit with terminating system according to the conventional art, it is necessary to provide the terminating resistors on the board. Thus, there is a problem in system cost and the like.